Instruction scheduling in compiler design. This allows the specific instructions to be written using high level programming constructs and frees the developer from worrying about calling conventions register allocation and instruction scheduling. Put more simply it tries to do the following without changing the meaning of the code. Srikant department of computer science indian institute of science bangalore 560 012 nptel course on compiler design yn. Csci 565 compiler design spring 2016 pedro diniz pedroatisiedu list scheduling algorithm idea.
Aug 07 2020 instruction scheduling compiler design computer science engineering computer science engineering cse video edurev is made by best teachers of computer science engineering cse. The pipeline stalls can be caused by structural hazards data hazards and control hazards. Another advantage to utilizing compiler intrinsics is that unlike standalone or inline assembly the compiler has visibility into what is occurring and perform further optimizations. Avoid pipeline stalls by rearranging the order of instructions.
Do a topological sorting of the dependence dag consider when an instruction can be scheduled without causing a stall schedule the instruction if it causes no stall and all its predecessors are already scheduled.